The Pins on the 8088 can be grouped into three categories:
1. Address and Data
2. Power and Timing
ADDRESS AND DATA
The address pins can be divided into three groups
AD0 – AD7
A8 – A15
A16 – A19
The reason for breaking them up like this is because not all of them carry the address all the time. Their portion of the address is valid during the beginning of each instruction cycle and the lines float when some other device takes control of the bus.
AD0 – AD7 : During the first part of an instruction cycle the 8088 puts the least significant (lower 8 bits) part of the address on these pins. When the CPU moves on to the 2nd part of the instruction cycle it removes the address from these lines and floats them. During the 3rd part of the instruction cycle it uses these pins as the data lines. Since data can go both ways – they are bidirectional during this part.
A8 – A15 : Are address only pins, and stay that way for the entire instruction cycle.
A16 – A19 : Carry valid address during the first part of an instruction cycle. Then carry status signals which indicate the address segment currently in use (S3 and S4), the state of the interrupts enable flag (S5) and a flag to indicate that the 8088 has control of the bus (S6)
POWER AND TIMING
The 8088 operates from a single +5 volt supply and the standard HMOS version can draw as much as 350ma.
There are two ground pins on the 8088, pin #1 and #20. It is important to note that these two pins are not electrically connected in the chip.
The voltage for Vcc should be 5 volts +/-10% and should be decoupled with a .1uf cap.
The 8088 only needs a single clock source fed into the CLK input. However, it has to be at a 33% duty cycle, with rise and fall times of no more than 10ns.
They make a chip for that, the 8284 – generates clock pulses for the 8088 – along with fully synchronized startup and manual reset as well. All in a 18pin Pdip package.
One thing to note – the 8088 registers are made from dynamic memory cells – they have to be refreshed. The minimum clock speed for any 8088 is 2Mhz. The max depends on the chip you are using.
The number of control signals available depends on if you operate the 8088 in the Minimum or maximum mode. This is done by Pin #33 – high min or low max.
Operating in maximum mode requires the use of another chip – the 8288 bus controller.
RD (active low) – indicates that the 8088 wants to read data from memory or I/O port. RD will remain high until the address is removed from the bus. RD will become low once the bus (AD0 -AD) floats. Once RD becomes low – the only bits on the bus are data.
The READY (#22) is the signal used by memory or I/O to let the 8088 know when the data operation is finished by pulling this line High.
For example – let’s suppose you are using a device that can’t transfer data fast enough to meet the 8088’s timing requirements. By pulling Ready low after the start of the T2 (when the AD0 – AD7 floats) clock cycle, the CPU will extend the machine cycle and wait until the READY line is high.
The INTR Pin (#18) Interrupt Request – The 8088 can be enabled with 256 vectored, prioritizes levels of interrupts. It looks at the INTR pin at the end of each instruction cycle. If the CPU sees that the line is active (HIGH) by a device it will jump to the subroutine whose address has been stored in memory lookup table.
This lookup table is fixed at locations, (00000h – 003FFh)
INTA (interrupts Acknowledge) pin is an output that becomes active low when an external device makes an interrupt request by pull INTR HIGH. When the 8088 receives this request, it will wait until the current instruction cycle is complete and puts out a low pulse on the INTA pin for two cycles.
On the 2nd cycle of this process – the device expects the device to have placed the interrupt level on the data bus.
TEST – is a way of stopping the 8088 until it is started again by some external event. If a WAIT instruction is issued, the 8088 will go into a state of (spaced out ness) until the TEST pin is brought low.
NMI Pin – Non-Maskable Interrupt – Active on low to high transition. Once active the 8088 will complete the current instruction and then jump to the NMI handling routine.
RESET Pin – Active high that stops the 8088. Has to stay HIGH for 4 clock cycles before the CPU floats the Address bus and do nothing, until the line is brought back LOW. Once LOW it will jump to address FFFF0H. (System re-start)
The MN/MX pin is used to set the CPU in either the Minimum (HIGH) or Maximum (Low) mode. If you are designing the system that has several CPUs accessing the address bus and data busses. When in max mode – you have to use the 8288 bus controller.
ALE – Address Latch Enable Pin. Remember the Address bus is split with the lower AD0 – AD7 used for Address and Data. How do we tell what state it is in. Enter the ALE, when HIGH the entire 20bit address is on the bus.
DEN – Data Enable – Active LOW – Tells the system that the data bus is available.
DT/R – Data Transmit / Receive – When DEN is LOW the system knows that the CPU is not using the data bus. DT/R tells the system if the CPU is expecting a device to send (LOW) or receive (HIGH)
IO/M – Input – Output Memory – Tells the system what type of transfer the CPU wants to do. HIGH tells the system the 8088 is talking to an IO port. LOW when working with system memory.
WR – Write – Active LOW signals to the system that the 8088 is during a write operation.
RD – Read – Active LOW signals to the system that the 8088 is during a read operation.
HOLD – Used by external devices when they want to get control of the system bus. Mainly used for DMA processes.
HLDA – Hold Acknowledge – HIGH when the 8088 has removed itself from the bus. The bus is floating at this point.
SSO – Status Signal Output – Used in combination with IO/M and DT/R to give a view into what the 8088 is doing on the bus, if anything.
Just to hit on the pins when setup in Maximum mode…
In Maximum mode – you can check the status of the instruction queue by looking at QS0 and QS1 (Queue Status)
S0, S1, S2 – Status are used by the 8288 Bus Controller to generate the control signals.
LOCK (Active LOW) is used in a muti-processor system to let the other processors know that using the bus is not a good idea.
RQ/GT0 – RQ/GT1 – Request Grant – act like the HOLD and HOLDA – They also let the 8088 share the bus with two external processors.