If you remember back – the clock input on the 8088 requires a 33% duty cycle. The 8284 Clock Generator can take care of this for us.
Here is the 8284 in all its glory..
(1) CSYNC – Clock Synchronization – An active HIGH signal which allows multiple 8284s to be synchronized. When CSYNC is low, the internal counters count, and when the counters are reset. CSYNC should be grounded when the internal oscillator is used.
(2) PCLK – TTL level clock for use with peripheral devices. This clock is 1/2 the frequency of CLK.
(3,7) ANE1, AEN2 – Address Enable – Active Low single is used to qualify its respective RDY inputs. If there
(4,6) RDY1, RDY2 – Bus Ready – This signal is sent to the 8284 from a peripheral device on the bus to indicate that data has been received or data is available to be read.
(5) READY – The READY signal to the processor is synchronized by the RDY inputs to the processor CLK. READY is cleared after the guaranteed hold time to the processor has been met.
(8) CLK – the Clock line to the processor. This is the MOS level clock output of 33% duty cycle to drive the cpu and bipolar support devices. The clock is 1/3 of the crystal or EFI frequency.
(9) GND – Ground Connections
(10) RESET – Is used to initialize the processor. Connects to reset on the processor
(11) RES – Reset in – triggers a device reset
(12) OSC – This TTL level clock is the output frequency of the oscillator circuit running at the crystal frequency.
(13) F/C – Frequency Crystal Select – Option used to select the clock source. HIGH for EFI , LOW for the crystal.
(14) EFI – External Frequency In – A square wave clock – three times the output of CLK.
(15) ASYNC – Asynchronous input – Ready Synchronization Select. ASYNC is an input active LOW that defines the synchronization model of the READY logic. When ASYNC is low, two stages of ready synchronization are provided. When ASYNC is left open or HIGH, a single stage of READY synchronization is provided.
(16,17) X2,X1 – Crystal IN
(18) VCC – Positive Rail in. +5