z80 pinout


Address and Data

A0 – A15 : Address Bus – Tri-state output, active high. A0-A15 constitute a 16-bit address bus. The address bus provides the address for memory (up to 64K bytes) data exchanges and for I/O device data exchanges. I/O addressing uses the 8 lower address bits to allow the user to directly select up to 256 input or 256 output ports. A0 is the least significant address bit. During refresh time, the lower7 bits contain a valid refresh address.

D0 – D7 : Data Bus – Tri-state input/ output, active high. D0-D7 constitute an 8-bit bidirectional data bus. The data bus is used for data exchanges with memory and I/O devices.

System Control

M1 : Machine Cycle 1 – Output, active low. Ml indicates that the current machine cycle is the OP code fetch cycle of an instruction execution. Note that during execution of 2-byte op-codes, Ml is generated as each op code byte is fetched These two byte op-codes always begin with CBH, DDH, EDH or FDH. MI also occurs with IORQ to indicate an interrupt acknowledge cycle.

MREQ : Memory Request – Tri-state output, active low. The memory request signal indicates that the address bus holds a valid address for a memory read or memory write operation.

IORQ : Input/Output Request – Tri-state output, active low. The IORQ signal indicates that the lower half of the address bus holds a valid I/O address for a I/O read or write operation. An IORQ signal is also generated with an Ml signal when an interrupt is being acknowledged to indicate that an interrupt response vector can be placed on the data bus. Interrupt Acknowledge operations occur during M1 time while I/O operations never occur during M1 time.

RD : Memory Read – Tri-state output, active low. RD indicates that the CPU wants to read data from memory or an I/O device. The addressed I/O device or memory should use this signal to gate data onto the CPU data bus.

WR : Memory Write – Tri-state output, active low. WR indicates that the CPU data bus holds valid data to be stored in the addressed memory or I/O device.

RFSH : Refresh – Output, active low. RFSH indicates that the lower 7 bits of the address bus contain a refresh address for dynamic memories and the current MREQ signal should be used to do a refresh read to all dynamic memories.

CPU Control

HALT : Halt State – Output, active low. HALT indicates that the CPU has executed a HALT software instruction and is awaiting either a non maskable or a maskable interrupt (With the mask enabled) before operation can resume. While halted, the CPU executes NOP’s to maintain memory refresh activity.

WAIT : Wait – Input, active low. WAIT indicates to the Z-80 CPU that the addressed memory or I/O devices are not ready for a data transfer. The CPU continues to enter wait states for as long as this signal is active. This signal allows memory or I/O devices of any speed to be synchronized to the CPU.

INT : Interrupt Request – Input, active low. The Interrupt Request signal is generated by I/O devices. A request will be honored at the end of the current instruction if the internal software controlled interrupt is enabled and if the BUSRQ signal is not active.

NMI : Non Maskable Interrupt – Input, negative edge triggered. The non maskable interrupt request line has a higher priority than INT and is always recognized at the end of the current instruction. NMI automatically forces the Z-80 CPU to restart to location 0066H.

RESET : Reset – Input, active low. RESET forces the program counter to zero and initializes the CPU.

Bus Control

BUSRQ : Bus Request – Input, active low. The bus request signal is used to request the CPU address bus, data bus and tri-state output control signals to go to a high impedance state so that other devices can control these buses. When BUSRQ is activated, the CPU will set these buses to a high impedance state as soon as the current CPU machine cycle is terminated.

BUSAK : Bus Acknowledge – Output, active low. Bus acknowledge is used to indicate to the requesting device that the CPU address bus, data bus and tri-state control bus signals have been set to their high impedance state and the external device can now control these signals.

CPU Clock and Power

CLOCK (pin 6) – Single phase TTL level clock
+5 (pin 11) – 5V@90mA